1. Field of the Invention
This invention relates to high-speed interfaces for computer network systems.
2. Description of the Background
When designing a high-speed interface between network components, there is typically a need for wrapping data back through transmitter and receiver circuitry. The wrapping back of data provides for verifying functionality as a “built in self test” (BIST). Preferably, a wrap path operates at functional speeds so that as much of the functional path as possible is used with out a performance penalty. One existing (prior art) approach for implementing the wrap path is depicted in FIG. 1.
Referring to FIG. 1, the illustration therein depicts prior art circuitry for verifying functionality of a high-speed interface implemented in a receive path 9. In this embodiment, a wrap path 5 for a receiver 8 is a mirror of a functional data path 6. The wrap path 5 is multiplexed in to the data path 6 after a second data receive stage. This design, or designs similar thereto, have typically been applied so that the data path 6 was not impaired by circuitry for the wrap path 5. Unfortunately, such designs have at least one drawback in that the actual circuitry of the data path 6 is not used. A second drawback is realized by having a multiplexer 4 in the data path 6, which causes added latency and jitter in a data signal.
What is needed is a high-speed interface between network components that provides for wrapping back of data and for verifying functionality thereof. Preferably, the high-speed interface makes use of an existing data path to provide for accurate communication, without causing latency and jitter in the data signal.